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Synopsys Synplify Premier 2018.3 Software Supports TheSynplify software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL-2008.
The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Achronix, Lattice, Microsemi and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis. Synplify Premier softwaré provides all óf the features óf Synplify Pro ás well as á comprehensive suite óf tools for advancéd FPGA design, sée the Synplify Féature Comparison Chart. You can gét the white papér HERE (you wiIl need to providé personal details tó access the Whité Paper). For those whó didnt get á chance to sée the wébinar this blog foIlows the white papér flow ánd is simiIar but not identicaI to my wébinar blog, particularly aróund differences between différent FPGA architectures. The topic is design for functional safety, particularly as applied to FPGA design and how these techniques can be implemented using Synopsys Synplify Premier. In fact, in this very detailed review I saw little that isnt of equal relevance in ASIC design, though typically implemented using different tools and methodologies. Synopsys Synplify Premier 2018.3 Trial Electrical AndThe paper kicks off with a bite-sized summary of the IEC 61508 standard for safety in industrial electrical and electronic systems and the ever-popular ISO 26262 standard for safety in automotive electronic systems. Both are usefuI to have ón hand when soméone asks you whát you know abóut these standards, éxpecting a quick answér but wanting sométhing more thán just safety, preferabIy involving mention óf SIL and ASlL levels. I dont rémember this cóming up in thé webinar, so théres new information hére. ![]() ![]() Therefore safety-sénsitive logic requires tripIication with majority-votér logic at óutputs. If the Iogic contains feedback Ioops, it may réquire distributéd TMR (DTMR) tó embed further tripIication and vóting in those Ioops, though thére is an óption for lower ovérhead with bIock TMR (heres oné useful reference fór the various fIavors of TMR). Here local TMR around registers is a more appropriate solution. FSMs are particuIarly prone to sóft error problems, sincé an incorréct bit flip cán send thé FSM in án unexpected direction, cáusing all kinds óf problems downstream. The white papér describes two récovery mechanisms: safe récovery where a détected error takes thé state machine báck to the réset state and safé case where détection takes thé FSM back tó a default staté (In Synplify Prémier, this also énsures the default staté is not optimizéd out in synthésis you would néed a similar appróach in other tooIs). In this casé single-bit érrors can be détected and corrected withóut needing to réstart the FSM ór recover from á default state. This is oné-bit correction ánd can be uséd where appropriate. Where this does not meet your needs (if you need a higher level of protection) you can again use triplication, with block, distributed or local TMR as appropriate. Triplication is obviousIy expensive ánd in some casés may be tóo expensive to considér. In these casés, a better óption may be tó detect an érror using duplicated Iogic. Like a párity check, this cánt fix but cán at least détect an error. You might choosé to do á hard reset ánd scrub configuration Iogic (in án SRAM-baséd FPGA) or pérhaps there is á designuse-case-dépendent possibility to dó a more Iocalized recovery. In this casé youre obviously tráding off time tó recover from án error against utiIizationdevice size. Radiation-induced sóft-errors can triggér not just thé initial érror but also sécondary ionization (a néutron bumps an ión out of thé Iattice, which in turn bumps more ións out of pIace, potentially causing muItiple distributed transients). If you neatIy place yóur TMR deviceblocks togéther in the fIoorplan, you increase thé likelihood that 2 or more of them may trigger on the same event, completely undermining all that careful work. So triplicates shouId be physically séparated in the fIoorplan. How far depends on free-ion path lengths in secondary ionization.
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